Additional information ...

.. in conjunction with the NOC Research Group @ IMD can be found in the following sections:

  • VLSI Tools
    Collection of tutorials and tools for VLSI design

  • Events
    List of conferences and events covering NOC and related topics

  • Links
    Collection of links (info resources, people ...)

VLSi Tools Setup: VLSI / EDA Design Environment

This section provides a tutorial for the setup and installation processes of a complete VLSI Design / EDA environment based on opensource hardware/software design and simulation tools. This environment generally addresses students at the Institute of Applied Microelectronics and Computer Engineering (IMD), other electronic design students and hobby designers who need a fully bundled tool suite for their electronic design projects or study works. The included tools support all major levels of modern electronic circuit design and most of them have already proven their productivity in real world projects. In details, the tool suite covers the following domains on hard- and software side:

  • Analog/Mixed Signal Design
  • Circuit & PCB Design
  • Circuit & Digital Logic Simulations
  • Digital IC Design
  • Embedded Systems Design
  • Eclipse IDE supporting Verilog, VHDL & SystemC

Moreover, this setup tutorial for the design environment targets a portable and flexible EDA solution without affecting an existing tool suite or configurations. For that purpose the installation on a virtual machine host represents the best way to go.

You can download the tutorial as a PDF file here.

Collection of related links

echnical resources:

  • OCP-IP: Interface socket for IPs
  • OCCN: Development framework for on-chip communication
  • OpenCores: Great collection of opensource IP cores (VHDL, Verilog & SystemC)
  • OpenCollector: Rich database about free opensource IP cores and EDA software tools
  • EDA: A great website about EDA standards, organizations and opensource tools

Literature sources:

Groups and People:

  • Nostrum: Developed at KTH Stockholm
  • xPipes: Joint project for NOC design and methodology
  • AEthereal: Publications page of Kees Goossens
  • QNoC: Project page of the Quality of service NOC (Technion)
  • Hermes: Project page of the Hermes NOC infrastructure
  • Atlas: An Environment for NOC generation and evaluation
  • NoCSim: A NOC Simulator

Events - List of ...

.. major conferences, workshops and all kinds of events related to NOCs. Covering system design, methodology and automation concepts, EDA-tools, software and technology:

Prospective aspects of Networks-on-Chip

The session "Prospective aspects of Networks-on-Chip" will be held as track area SS2 at the Euromicro Conference on Digital System Design (DSD 2008, 3-5 September, Parma, Italy).

Accepted papers and posters in the various tracks:

  • Large Scale On-Chip Networks: An Accurate Multi-FPGA Emulation Platform, Abdellah Medjadji Kouadri Mostéfaoui, Benaoumeur Senouci and Frédéric Pétrot
  • Network Interface Sharing Techniques for Area Optimized NoC Architectures, Davide Bertozzi, Simone Medardoni and Alberto Ferrante
  • Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links, Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar and Vincenzo Catania
  • CART: Communication-Aware Routing Technique for Application-Specific NoCs, Juan Manuel Orduña, Rafael Tornero, Andrés Mejía, José Flich and José Duato
  • LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control, Sergio Saponara, Francesco Vitullo, Riccardo Locatellli, Philippe Teninge, Marcello Coppola and Luca Fanucci
  • An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures, Thomas J Sødring, Åshild Grønstad Solheim, Tor Skeie and Sven-Arne Reinemo
  • A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips, Markus Winter and Gerhard Fettweis
  • A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching, Simone Secchi, Francesca Palumbo, Danilo Pani and Luigi Raffo

Program committee

  • C. Cornelius, U. of Rostock (DE)   [Session chair]
    M. Coppola, ST Microelectronics (FR)
    L. Gomes, U. of Lisbon (PT)
    K. Goossens, NXP Semiconductors (NL)
    L. Jóźwiak, Eindhoven U. of Technology (NL)
    S. Kubisch, U. of Rostock (DE)
    S. Kumar, U. of Jönköping (SE)
    G. Lemieux, U. of British Columbia (CA)
    S. Saponara, U. of Pisa (IT)
    D. Timmermann, U. of Rostock (DE)
    F. Tobajas, U. of Las Palmas (ES)

The proceedings of the DSD'2008 will be published by the IEEE Computer Society.

Background

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded) digital and mixed hardware/software system engineering. It is a discussion forum for researchers and engineers working on state-of-the-art investigations, development and applications. It focuses on advanced system and design automation concepts, paradigms, methods and tools, as well as modern implementation technologies that enable effective and efficient development of high-quality (embedded) systems for important and demanding applications in fields such as (wireless) communication and networking, measurement and instrumentation, healthcare and medicine, military, space, avionic and automotive systems, security, multimedia and ambient intelligence.

Networks-on-Chip (NOC) have been proposed as a new paradigm to cope with the increasing issues of system design in nanotechnology. By now, fundamental components have been developed and their functionality has been proven. However, many issues still have to be solved to allow the application in practice in terms of system performance as well as support for cost-effective development. The importance of NOC in industry and academia has also been reflected in the success of this special session in the past two confereces (DSD 2006 and DSD 2007). Thus, we decided to continue this type of platform to exchange ideas and stimulate new findings within this challenging field of research.

Scope

This special session addresses all aspects related to concepts, implementations and applications of networks-on-chip as well as related EDA tools. Nonetheless, its focus is on prospective issues and interdisciplinary topics like reliability, system control, design flow, application studies and the outlook on future developments in NOC design.
Papers on any of the following and related topics will be considered for the special session:

 

  • Advanced concepts and architectures: Links, Routers, Topology
  • Reconfiguration and Hardwired NOCs on FPGAs
  • Programming models, Application mapping, Benchmarking
  • Operating systems and System control
  • Reliability, Fault-tolerance, Robustness
  • Verification and Testability
  • Design flow and Design space exploration
  • Prototypes and Application studies

Advanced issues of Networks-on-Chip

The session "Advanced issues of Networks-on-Chip" will be held as track area SS2 at the Euromicro Conference on Digital System Design (DSD 2007, 27-31 August, Luebeck, Germany).

Accepted papers and posters for the sessions:

  • GigaNoC ? A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors, Christoph Puttmann, Jörg Niemann, Mario Porrmann and Ulrich Rückert
  • On network-on-chip comparison, Erno Salminen, Ari Kulmala and Timo Hämäläinen
  • Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy, Mikael Millberg, Axel Jantsch
  • Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer, D. Mangano, G. Falconeri, C. Pistritto and A. Scandurra
  • Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures, Timo Schönwald, Jochen Zimmermann, Oliver Bringmann and Wolfgang Rosenstiel
  • On-Chip Verification of NoCs Using Assertion Processors, Mohammad Kakoee, M. Neishaburi, M. Daneshtalab, Saeed Safari and Zainalabedin Navabi
  • Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations, Leandro Fiorin and Cristina Silvano
  • NoC Topologies Exploration based on Mapping and Simulation Models, Luciano Bononi, Nicola Concer and Miltos Grammatikakis
  • Application-Specific Topology Design Customization for STNoC, Gianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli and Marcello Coppola
  • Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip, Pekka Rantala, Jouni Isoaho and Hannu Tenhunen
  • On the Impact of Serialization on the Cache Performances in Network-on-Chip based MPSoCs, Paolo Meloni, Giovanni Busonera, Salvatore Carta and Luigi Raffo

The proceedings of the DSD'2007 will be published by the IEEE Computer Society.

Background

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded) digital and mixed hardware/software system engineering. It is a discussion forum for researchers and engineers working on state-of-the-art investigations, development and applications. It focuses on advanced system and design automation concepts, paradigms, methods and tools, as well as modern implementation technologies enabling an effective and efficient development of high-quality systems for important and demanding applications in fields such as communication and networking, measurement and instrumentation, healthcare and medicine, military, space, avionic and automotive systems, security, multimedia and ambient intelligence.

Networks-On-Chip (NOC) have been proposed as a new system paradigm to cope with those increasing issues of nanotechnology. Thereby, modularity and parallelism are the two most promising characteristics of such systems. NOCs consist of independent computation units that might work with different voltages, frequencies or even diverse technologies. Communication between these units is enabled by on-chip networks that allow the concurrent transmission of data.

Scope

This special session addresses all aspects related to concepts, implementations and applications of networks-on-chip as well as related EDA tools. Nonetheless, its focus is on advanced issues and interdisciplinary topics like system control, design flow, application studies and the outlook on future developments in NOC design.
Papers on any of the following and related topics will be considered for the special session:

 

  • Future concepts and architectures: Links, Routers, Topology
  • Reconfiguration and Hardwired NOCs on FPGAs
  • Programming models, Application mapping, Benchmarking
  • Operating systems and System control
  • Reliability, Fault-tolerance, Robustness
  • Verification and Testability
  • Design flow and Design space exploration
  • Prototypes and Application studies

 

Program committee

  • C. Cornelius, U. of Rostock (DE)   [Session chair]
    R. Drechsler, U. of Bremen (DE)
    L. Jóźwiak, Eindhoven U. of Technology (NL)
    S. Kubisch, U. of Rostock (DE)
    G. Lemieux, U. of British Columbia (CA)
    F. Moraes, PUCRS (BR)
    F. Tobajas, U. of Las Palmas (ES)
    H. Tenhunen, KTH (SE)
    D. Timmermann, U. of Rostock (DE)

Additional support is gratefully acknowledged:
Shashi Kumar, U. of Jönköping (SE)
Christian Neeb, U. of Kaiserslautern (DE)

Low-Power and High-Performance Networks-on-Chip

The session "Low-Power and High-Performance Networks-on-Chip" will be held as track area SS2 at the Euromicro Conference on Digital System Design (DSD 2006, 30. August - 1. September, Cavtat, Croatia).

Accepted papers for the special session:

  • Adaptive Power Management for the On-Chip Communication Network
  • A simple clockless Network-on-Chip for a commercial audio DSP chip
  • Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
  • Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip
  • Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm
  • Packetizing OCP Transactions in the MANGO Network-on-Chip
  • Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions
  • A High Level Power Model for the Nostrum NoC
  • Off-line Testing of Delay Faults in NoC Interconnects

Further interesting papers on Networks-on-Chip:

  • Towards Performance-oriented Pattern-based Refinement of Synchronous Models onto NoC Communication
  • Resource-efficient Routing and Scheduling of Time-constrained Network-on-Chip Communication
  • On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures

The Proceedings of the DSD'2006 will be published by the IEEE Computer Society.

 

Background

The Euromicro Conference on Digital System Design addresses all aspects of (embedded) digital and mixed hardware/software system engineering. It is a discussion forum for researchers and engineers working on state-of-the-art investigations, development, and applications. It focuses on advanced system, design, and design automation concepts, paradigms, methods and tools, as well as, modern implementation technologies that enable effective and efficient development of high-quality (embedded) systems for important and demanding applications in fields such as (wireless) communication and networking; measurement and instrumentation; health-care and medicine; military, space, avionic and automotive systems; security; multi-media and ambient intelligence.

Modern highly integrated systems face several severe problems: on-chip interconnection and communication problems, power and energy crisis, decreased reliability, to mention just a few. Network-on-Chip, consisting of relatively independent communicating sub-systems that might work with different voltages, frequencies, or even diverse technologies, and isolating computation and communication from each other, promises solutions for some of these issues.

Scope

Although this special session addresses all aspects related to concepts, implementations and applications of networks-on-chip and related EDA tools, its focus is on low-power and high-performance aspects.
Papers on any of the following and related topics will be considered for the special session:

  • Network-on-Chip concepts and architectures
  • Application-specific communication on a chip and network topology
  • Routing schemes, switch concepts, layouts, and signal transmission
  • Low-power, low-energy and high-performance computation and communication
  • Communication/computation and energy/performance trade-offs
  • Static power minimization and dynamic power management
  • Data coding, error detection, fault-tolerance and robustness
  • Prototypes and applications

 

Program committee 

  • C. Cornelius, U. of Rostock (DE)
    L. Jóźwiak, Eindhoven U. of Technology (NL)
    A. Nunez, U. Las Palmas (ES)
    F. Sill, U. of Rostock (DE)
    D. Timmermann, U. of Rostock (DE)

Important links

EUROMICRO web page:    http://www.euromicro.org