Johannes Knödtel

Johannes Knödtel
Tel.: +49 381 498 7293
Raum: 106


  • Integrierte Systeme


Vor Juli 2023

Johannes Knödtel and Marc Reichenbach:
Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration
In DroneSE and RAPIDO: System Engineering for constrained embedded systems, pages 60–65, Toulouse France, January 2023. ACM. ISBN 9798400700453. doi: 10.1145/3579170.3579257. URL

Christian Scheibe, Ananya Kuri, Yuyao Feng, Le Zhao, Xuejun Xiong, Piergiovanni La Seta, Xiao Peng Liang, Johannes Knödtel, Philipp Holzinger, Marc Reichenbach, and Gert Mehlmann:
Interfacing real-time and offline power system simulation tools using UDP or FPGA systems
Electric Power Systems Research, 212:108490, November 2022. ISSN 03787796. doi: 10.1016/j.epsr.2022.108490. URL

Johannes Knödtel, Sebastian Rachuj, and Marc Reichenbach:
Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?
In 2022 25th Euromicro Conference on Digital System Design (DSD), pages 247–253, Maspalomas, Spain, August 2022. IEEE. ISBN 978-1-66547-404-7. doi: 10.1109/DSD57027.2022.00041. URL

Markus Fritscher, Johannes Knödtel, Maen Mallah, Stefan Pechmann, Emilio Perez-Bosch Quesada, Tommaso Rizzi, Christian Wenger, and Marc Reichenbach:
Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks
In Alex Orailoglu, Matthias Jung, and Marc Reichenbach, editors, Embedded Computer Systems: Architectures, Modeling, and Simulation, volume 13227, pages 401–417. Springer International Publishing, Cham, 2022. ISBN 978-3-031-04579-0 978-3-031-04580-6. doi: 10.1007/978-3-031-04580-6\27. URL Series Title: Lecture Notes in Computer Science

Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, and Dietmar Fey:
RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems
IEEE Access, 9:43684–43700, 2021. ISSN 2169-3536. doi: 10.1109/ACCESS.2021.3063238. URL

Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, and Marc Reichenbach:
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
In 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), pages 1–4, Arequipa, Peru, February 2021. IEEE. ISBN 978-1-72817-670-3. doi: 10.1109/LASCAS51355.2021.9459159. URL

Johannes Knödtel, Markus Fritscher, Daniel Reiser, Dietmar Fey, Marco Breiling, and Marc Reichenbach:
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories
In 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST), pages 1–6, Bremen, Germany, September 2020. IEEE. ISBN 978-1-72816-687-2. doi: 10.1109/MOCAST49295.2020. 9200241. URL

Jakob Peschel, Johannes Knödtel, Eduardo Pérez, Marc Reichenbach, Christian Wenger, and Dietmar Fey:
Optimizing Multi-State Reliability in ReRAM Arrays using an Automated Device Selection Method
July 2019

Markus Fritscher, Johannes Knödtel, Marc Reichenbach, and Dietmar Fey:
Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools
In 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pages 225–228, Genoa, Italy, November 2019. IEEE. ISBN 978-1-72810-996-1. doi: 10.1109/ICECS46596.2019.8964856. URL

Daniel Wust, Dietmar Fey, and Johannes Knödtel:
A programmable ternary CPU using hybrid CMOS/memristor circuits
International Journal of Parallel, Emergent and Distributed Systems, 33(4):387–407, July 2018. ISSN 1744-5760, 1744-5779. doi: 10.1080/17445760.2017.1422251. URL

Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, and Dietmar Fey:
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs
In 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 46–53, Platja d’Aro, July 2018. IEEE. ISBN 978-1-5386-6365-3. doi: 10.1109/PATMOS.2018.8464149. URL

Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach, Christopher Soll, and Dietmar Fey:
Prototyping memristors in digital system with an FPGA-based testing environment
In 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 1–7, Thessaloniki, September 2017. IEEE. ISBN 978-1-5090-6462-5. doi: 10.1109/PATMOS.2017.8106978. URL

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