Introduction ...

... of the involved people contributing their time and effort to the NOC Research Group @ IMD:

• Jonas Kutzner, May 2012
  Design Space Exploration for Multiprocessor Approaches based on ASIPs
• Erik Sander, April 2012
  Analysis of register file performance and approaches to reduce the power dissipation
• Robert Gubitz, September 2011
  Implementation of a Hardware/Software approach for the control of online tests and fault diagnosis
• Björn Konieczek, September 2011
  Design and evaluation of a software module for the determination of routing paths in Networks-On-Chip
• Tino Demuth, April 2010
  Development and Implementation of a Low-Power TMR design
• Sven Poeggel, September 2009
  Modelling of temperature distributions in on-chip networks
• Tim Wegner, October 2009
  Concept and Integration of components to increase the Reliability in Networks-on-Chip
• Andy Seidel, October 2009
  Development of a graphical user interface for the configuration of network-on-chip simulations
• Tino Demuth, August 2009
  Enhancing router characteristics of an on-chip Network during Synthesis and Layout
• Korinna Brackebusch, April 2009
  Analysis of causes and solutions to cope with reliability of signal transmission in nanometer technology
• Jónatan Muñoz Gelde, June 2009
  Impact of traffic patterns and application mapping on multi-processor systems based on networks-on-chip
• Matthias Hinkfoth, April 2009
  Characterization of a 65 nm technology against the background of parameter variations
• Helge Ecklebe, February 2009
  Analysis of causes and solutions to cope with reliability of signal transmission in nanometer technology
• Enrico Daum, October 2008
  Development and analysis of different approaches to improve performance characteristics of the system-internal communication of a NoC-based system
• Frank Pribbernow, April 2008
  Realization of a router for on-chip networks with optimized power consumption and reliability
• Tino Demuth, December 2007
  Analysis of the Development of Network-on-Chip Technology over the last couple of Years
• Sören Sofke, November 2007
  Implementation and comparison of different router concepts for on-chip networks
• Enrico Heinrich, October 2007
  Modifications on an existing NoC for mesochronous GALS Operation
• Sara Hernandez, September 2007
  Application Mapping onto a NoC Grid
• Andy Strzeletz, May 2007
  Specification and Implementation of a Simulation IP Core for application-specific NoC Performance Evaluation
• Frank Pribbernow, August 2007
  Router/Switch-Architectures for Networks-on-Chip under Low-power aspects
• Hagen Sämrow, August 2007
  Investigation of Influences from Technology and Layout on Signal Transmission in Nanotechnology
• Tim Eickelberg, March 2007
  Analysis of current-sensing methods for the acceleration of signal transmissions in nanotechnology
• Jiaxi You, December 2006
  High-level simulation of on-chip networks for benchmarking and application mapping
• Enrico Heinrich, December 2006
  Implementation and analysis of virtual channels in a two-dimensional NOC grid
• Tim Eickelberg, November 2006
  Application of boosters to accelerate signal transmission in nanometer-technologies
• Mathias Rulf, October 2006
  Signal transmission with repeaters in nanometer-technologies
• Martin Siemroth, May 2006
  Creation of an environment for SystemC/VHDL Co-simulation of Networks-on-Chip
• Andreas Herrholz, January 2006
  Concept and design of the transport-layer for Networks-on-Chip in dynamically reconfigurable Systems
• Elmar Zeeb, September 2005
  Enhancement of a Linux Operating Sytem for the management of dynamically reconfigurable hardware
• Harald Michelsen, September 2005
  Application design for Network-on-Chip based dynamically reconfigurable Systems
• Andreas Herrholz, January 2005
  Development of a SystemC module library for the behaviroal simulation of Networks-on-Chip
• Harald Michelsen, August 2004
  Concept and implementation of BSD socket-based protocol stack for Network-on-Chip
• Marco Kluge, June 2004
  Concept and design of a Hardware/Software Interface for reconfigurable Systems-on-Chip
• Elmar Zeeb, June 2004
  Conceptual design of a Linux based Operating System for reconfigurable Logic